This invention pertains to a multiprocessing interrupt arrangement which eliminates the need for hardwired interrupt signaling paths between processors and also eliminates special bus cycles for sending interrupts between processors.
Multiprocessing has become a standard technique in telephone and computing systems for allowing a large number of independent processes to occur simultaneously, each having minimal need to communicate with the other. In such multiprocessing systems problems exist in that it is often necessary to have one independent processor interrupt another one of the processors in the network. Such interrupts are used, for example, to change the task of the other processor.
Three basic approaches are presently being used. These are (1) fully interconnected network of interrupts, (2) unique system bus cycles, and (3) polling of flags in local memory.
In the first arrangement, there is a unique interrupt signal from each processor in the network to the other processors. For large systems the number of interrupt connections becomes unwieldy. The second approach requires additional signal paths between processors to distinguish interrupt cycles from normal memory transfer cycles. The third approach requires each processor to regularly poll specific memory locations to ascertain whether or not it has been interrupted.